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ADIAD9268系列16位125MSPS模数转换方案

2017-11-23 06:48 PM| 发布者: 噗噗东| 查看: 3074| 评论: 0

摘要: ADI公司的AD9268系列是16位80MSPS/105MSPS/125MSPS双路1.8V模数转换器(ADC),支持高性能低本钱小尺寸和多样化的应用.70MHz和125MSPS时的SNR=78.2dBFS,SFDR=88dBc,功耗为750mW,.8V模拟电压,1.8VCMOS或LVDS输出电源,IF ...

ADI公司的AD9268系列是16位80 MSPS/105 MSPS/125 MSPS 双路1.8V模数转换器(ADC),支持高性能低本钱小尺寸和多样化的应用. 70 MHz 和125 MSPS时的SNR=78.2 dBFS, SFDR = 88 dBc,功耗为750mW,.8V模拟电压, 1.8 V CMOS或LVDS输出电源,IF取样频率高达300MHz,小信号输入噪音为−153.6 dBm/Hz,主要用于通信,多功能无线电系统,3G吸收器, GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA以及智能天线系统,通用软件无线电,超声波设备以及宽带数据应用.本文先容AD9268主要特点, 功能方框架图以及评估板毗连框架图,电路图以及质料清单(BOM).

AD9268:16-Bit,80 MSPS/105 MSPS/125 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC)

The AD9268 is a dual, 16-bit, 80 MSPS/105 MSPS/125 MSPS analog-to-digital converter (ADC). The AD9268 is designed to support communications applications where high performance, combined with low cost, small size, and versatility, is desired.

The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth, differential sample-and-hold analog input amplifiers that support a variety of user-selectable input ranges. An integrated voltage reference eases design consid-erations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.

The ADC output data can be routed directly to the two external 16-bit output ports. These outputs can be set to either 1.8 V CMOS or LVDS. Flexible power-down options allow significant power savings, when desired. Programming for setup and control is accomplished using a 3-wire SPI-compatible serial interface.

The AD9268 is available in a 64-lead LFCSP and is specified over the industrial temperature range of −40℃ to +85℃.

AD9268主要特点:

SNR = 78.2 dBFS @ 70 MHz and 125 MSPS

SFDR = 88 dBc @ 70 MHz and 125 MSPS

Low power: 750 mW @ 125 MSPS

1.8 V analog supply operation

1.8 V CMOS or LVDS output supply

Integer 1-to-8 input clock divider

IF sampling frequencies to 300 MHz

−153.6 dBm/Hz small-signal input noise with 200 Ω input impedance @ 70 MHz and 125 MSPS

Optional on-chip dither

Programmable internal ADC voltage reference

Integrated ADC sample-and-hold inputs

Flexible analog input range: 1 V p-p to 2 V p-p

Differential analog inputs with 650 MHz bandwidth

ADC clock duty cycle stabilizer

95 dB channel isolation/crosstalk

Serial port control

User-configurable, built-in self-test (BIST) capability

Energy-saving power-down modes

PRODUCT HIGHLIGHTS

On-chip dither option for improved SFDR performance with low power analog input.

Proprietary differential input that maintains excellent SNR performance for input frequencies up to 300 MHz.

Operation from a single 1.8 V supply and a separate digital output driver supply accommodating 1.8 V CMOS or LVDS outputs.

Standard serial port interface (SPI) that supports various product features and functions, such as data formatting (offset binary, twos complement, or gray coding), enabling the clock DCS, power-down, test modes, and voltage reference mode.

Pin compatibility with the AD9258, allowing a simple migration from 16 bits to 14 bits. The AD9268 is also pin compatible with the AD9251, AD9231, and AD9204 family of products for lower sample rate, low power applications.

AD9268应用:

Communications

Diversity radio systems

Multimode digital receivers (3G)

GSM, EDGE, W-CDMA, LTE,

CDMA2000, WiMAX, TD-SCDMA

I/Q demodulation systems

Smart antenna systems

General-purpose software radios

Broadband data applications

Ultrasound equipment

图1.AD9268功能方框架图

Evaluating the AD9268/AD9258/AD9251/AD9231/AD9204 Analog-to-Digital Converters

This document describes the AD9268, AD9258, AD9251, AD9231, and AD9204 evaluation board, which provides all of the support circuitry required to operate the AD9268, AD9258, AD9251, AD9231, or AD9204 in their various modes and configurations. The application software used to interface with the devices is also described.

AD9268系列评估板主要特点:

Full featured evaluation board for the AD9268/AD9258/AD9251/AD9231/AD9204
SPI interface for setup and control

External, on-board oscillator, or AD9517 clocking options

Balun/transformer or amplifier input drive options

LDO regulator or switching power supply options

VisualAnalog® and SPI controller software interfaces

EQUIPMENT NEEDED

Analog signal source and antialiasing filter

Sample clock source (if not using the on-board oscillator)

2 switching power supplies (6.0 V, 2.5 A), CUI EPS060250UH-PHP-SZ, provided

PC running Windows® 98 (2nd ed.), Windows 2000, Windows ME, or Windows XP

USB 2.0 port, recommended (USB 1.1 compatible)

AD9268, AD9258, AD9251, AD9231, or AD9204 evaluation board

HSC-ADC-EVALCZ FPGA-based data capture kit

SOFTWARE NEEDED

VisualAnalog

SPI controller

图2. AD9268和AD9251系列评估板与HSC-ADC-EVALCZ 数据捕获板外形图

图3.评估板毗连框架图

图4. AD9268评估板输入和电源电路图

图5. AD9268评估板DUT和相关电路图

图6. AD9268评估板SPI接口电路图

图7. AD9268评估板通路A输入电路图

图8. AD9268评估板通路B输入电路图

图9. AD9268评估板默认时钟通路输入电路图

图10. 可选择AD9517时钟输入电路图

图11. AD9268评估板输出缓冲器电路图

图12. AD9268评估板FIFO板毗连器毗连图

AD9268 系列BOM




AD9251 系列BOM




详情请复制打开此衔接地址:
http://www.analog.com/static/imported-files/user_guides/UG-003.pdf

http://www.analog.com/static/imported-files/data_sheets/AD9268.pdf


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