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Lattice LPTM10-12107平台电源管理开发方案

2017-11-24 05:27 PM| 发布者: 久伴我心的海角| 查看: 201| 评论: 0

摘要: lattice 公司的平台电源管理器件包括连个器件: LPTM10-1247和LPTM10-12107,LPTM10-1247能监视12个电压源,支持47个数字输入和数字输出组合,而LPTM10-12107监视多达12个电压源,支持107个数字输入和数字输出组合.两个器 ...
lattice 公司的平台电源管理器件包括连个器件: LPTM10-1247和LPTM10-12107,LPTM10-1247能监视12个电压源,支持47个数字输入和数字输出组合,而LPTM10-12107监视多达12个电压源,支持107个数字输入和数字输出组合.两个器件包括电源管理部分和数字板级电源管理部分.电源管理部分包括可编程阈值,精度0.7%的差分输入比较器,10位ADC和用来调整电源和富余量的可调整区块;数字板级电源管理部分由640-LUT FPGA和可编程逻辑接口I/O组成,典型应用包括无线基础设备,网络核心设备,服务器,数据存储和高端工业仪表等.本文介绍了LPTM10-12107主要特性,方框图,平台管理典型应用框图以及平台电源管理和数字功能方框图, 平台电源管理评估板电路图和材料清单(BOM).

The Platform Manager product family consists of two devices, the LPTM10-1247 and LPTM10-12107. The LPTM10-1247 device can monitor 12 voltage rails and supports 47 combined digital inputs and digital outputs, while the LPTM10-12107 monitors up to 12 voltage rails and supports 107 combined digital inputs and digital outputs. Functionally, these devices include both a power management section and a digital board management section. The power management section consists of a programmable threshold, precision differential input comparator block with an accuracy of 0.7%, a 48-macrocell CPLD, programmable hardware timers, a 10-bit analog to digital converter and a trim block for the trimming and margining of supplies. The digital board management section consists of a 640-LUT FPGA and programmable logic interface I/O.

The Lattice Platform Manager integrates board power management (hot-swap, sequencing, monitoring, reset generation, trimming and margining) and digital board management functions (reset tree, non-volatile error logging, glue logic, board digital signal monitoring and control, system bus interface, etc.) into a single chip. The Platform Manager device provides 12 independent analog input channels to monitor up to 12 power supply test points. Up to 12 of these input channels can be monitored through differential inputs to support remote ground sensing. Each of the analog input channels is monitored through two independently programmable comparators to support both high/low and in-bounds/ out-of-bounds (window-compare) monitor functions. Up to six general purpose 5V tolerant digital inputs are also provided for miscellaneous control functions. There are 16 open-drain digital outputs that can be used for controlling DC-DC converters, low-drop-out regulators (LDOs) and opto-couplers, as well as for supervisory and general purpose logic interface functions. Four of these outputs (HVOUT1-HVOUT4) may be configured as high-voltage MOSFET drivers. In highvoltage mode these outputs can provide up to 12V for driving the gates of n-channel MOSFETs so that they can be used as high-side power switches controlling the supplies with a programmable ramp rate for both ramp up and ramp down.

The board power management function can be implemented using the on-chip 48-macrocell CPLD. The status of all of the comparators on the analog input channels as well as the general purpose digital inputs are used as inputs by the CPLD array, and all digital outputs (open-drain as well as HVOUT) may be controlled by the CPLD. Four independently programmable timers can create delays and time-outs ranging from 32 s to 2 seconds. The Platform Manager device incorporates up to eight DACs for generating trimming voltage to control the output voltage of a DC-DC converter. Additionally, each power supply output voltage can be maintained typically within 0.5% tolerance across various load conditions using the Digital Closed Loop Control mode. The on-chip 10-bit A/D converter can both be used to monitor the VMON voltage through the I2C bus as well as for implementing digital closed loop mode for maintaining the output voltage of all power supplies controlled by the monitoring and trimming section of the Platform Manager device. The FPGA section of the Platform Manager is optimized to meet the requirements of board management functions including reset distribution, boundary scan management, fault logging, FPGA load control, and system bus inter-face. The FPGA section uses look-up tables (LUTs) and distributed memories for flexible and efficient logic imple-mentation. This instant-on capability enables the Platform Manager devices to integrate control functions that are required as soon as power is applied to the board. Power management functions can be integrated into the CPLD and digital board management functions can be integrated into the FPGA using the LogiBuilder tool provided by PAC-Designer® software. In addition, the FPGA designs can also be implemented in VHDL or Verilog HDL through the ispLEVER® software design tool. The Platform Manager IC supports a hardware I2C/SMBus slave interface that can be used to measure voltages through the Analog to Digital Converter or is used for trimming and margining using a microcontroller. There are two JTAG ports integrated into the Platform Manager device: Power JTAG and FPGA JTAG. The Power JTAG interface is used to program the power section of the Platform Manager and the FPGA JTAG is used to con-figure the FPGA portion of the device. The FPGA configuration memory can be changed in-system without inter-rupting the operation of the board management section. However, the Power Management section of the platform Manager cannot be changed without interrupting the power management operation.

Platform Manager Family Selection Table

LPTM10-12107主要特性:

Precision Voltage Monitoring Increases Reliability

• 12 independent analog monitor inputs

• Differential inputs for remote ground sense

• Two programmable threshold comparators per analog input

• Hardware window comparison

• 10-bit ADC for I2C monitoring

High-Voltage FET Drivers Enable Integration

• Power supply ramp up/down control

• Programmable current and voltage output

• Independently configurable for FET control or digital output

Power Supply Margin and Trim Functions

• Trim and margin up to eight power supplies

• Dynamic voltage control through I2C

• Independent Digital Closed-Loop Trim function for each output

Programmable Timers Increase Control Flexibility

• Four independent timers

• 32 us to 2 second intervals for timing sequences

PLD Resources Integrate Power and Digital Functions

• 48-macrocell CPLD

• 640 LUT4s FPGA

• Up to 107 digital I/Os

• Up to 6.1 Kbits distributed RAM

Programmable sysIO™ Buffer Supports a Range of Interfaces

• LVCMOS 3.3/2.5/1.8/1.5/1.2

• LVTTL

System-Level Support

• Single 3.3V supply operation

• Industrial temperature range: -40°C to +85°C

In-System Programmability Reduces Risk

Integrated non-volatile configuration memory

• JTAG programming interface

Package Options

• 128-pin TQFP

• 208-ball ftBGA

• RoHS compliant lead-free and halogen-free

图1.LPTM10-12107方框图

图2.LPTM10-12107典型的平台管理应用框图

Thank you for choosing the Platform Manager™ Development Kit. This user’s guide describes how to start using the Platform Manager Development Kit, an easy-to-use system for evaluating and designing with the Platform Man­ager mixed-signal device. The kit serves as a development test environment to build designs for power supply man­agement functions such as sequencing, power supply fault logging, trimming, reset generation, high-side MOSFET drive and user logic I/O expansion in an FPGA.

平台管理开发套件主要特性:

The Platform Manager Development Kit includes:

• Platform Manager Evaluation Board containing the Platform Manager LPTM10-12107 device in a 208-ball ftBGA package

• USB programming support on-board

• 4Mbit SPI Flash memory for logging data and faults

• SPI and I2C interfaces

• 2x16 expansion header for I2C, SPI and general purpose data bus, I/O

• Two 4-bit DIP switches

• Three push-buttons for input control, reset, etc.

• DAC and A/D convertors for trimming power supplies

• LED displays

• LCD display

• Adjustable potentiometers for user faults or demos

• Thermistor circuit for temperature sensing

• LDO to demo sequencing and trim functions

• DC-DC convertor to demo sequencing and trim functions

• Two LDOs for main chip power and VCCIO supplies.

• VMON, voltage monitors for on-board and off-board power supply monitoring • Off-board screw connectors for user loads and testing

• Prototyping/interface connections

• Pre-loaded Demo – The Platform Manager Development Kit contains a pre-loaded demo design that illustrates many of the key features of the Platform Manager device.

• USB Connector Cable – The Platform Manager Evaluation Board is programmed via the USB cable driven from the user’s computer. This USB cable is included in the Platform Manager Development Kit.

• Power Supply – The Platform Manager Evaluation board is powered by an AC adapter (included).

图3.平台管理评估板外形图(顶视图)
 
图4.平台电源管理和数字功能方框图

图5.平台管理评估板电路图:Mux

图6.平台管理评估板电路图:Bank0, Bank3

图7.平台管理评估板电路图:LPTM10-12107-DEC-EVN

图8.平台管理评估板电路图:插座

图9.平台管理评估板电路图:JTAG数据链

图10.平台管理评估板电路图:LCD Bank

图11.平台管理评估板电路图:LEDs

图11.平台管理评估板电路图:CPLD输出

图12.平台管理评估板电路图:USB Section5

图13.平台管理评估板电路图:板电源

图14.平台管理评估板电路图:用户电源

图15.平台管理评估板电路图:SPI Flash Fan Pads5

图16.平台管理评估板电路图:DIP开关

图17.平台管理评估板电路图:VMONs, DACs, Slide Potentiometer
平台管理开发套件材料清单(BOM):


详情请见:
http://www.latticesemi.com/documents/DS1036.pdf

http://www.latticesemi.com/documents/EB58.pdf

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